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LTC3447 I2C Controllable Buck Regulator in 3mm x 3mm DFN

I2C Programmable Output with 21.6mV Resolution Overtemperature Protected High Efficiency: Up to 93% Very Low Quiescent Current: Only 33A 600mA Output Current at VIN = 3V 2.5V to 5.5V Input Voltage Range 1MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle Stable with Ceramic Capacitors Shutdown Mode Draws <1A Supply Current 2% Output Voltage Accuracy Standard (100kHz) or Fast Mode (400kHz) I2C 6-Bit Voltage DAC (0.69V to 2.05V) Disable Burst Mode Operation Enable Power Good Blanking Optional External Start-Up Resistors Soft-Start 10 Lead, 3mm x 3mm DFN Package Distributed Power Supplies Notebook Computers PDAs and Other Handheld Devices
The LTC(R)3447 is a high efficiency monolithic synchronous current mode buck regulator. Using an I2C interface, the output voltage can be set between 0.69V and 2.05V using an internal 6-bit DAC. The buck regulator has optional external feedback resistors that can be used for setting the initial start up voltage. The feedback voltage reference for this start-up option is 0.6V. Once the voltage DAC is updated via the I2C, the buck regulator switches from external to internal feedback resistors. When there are no external resistors, the default start-up voltage is 1.38V. The switching frequency is internally set at 1MHz, allowing the use of small surface mount inductors and capacitors. In Burst Mode(R) operation, supply current is only 33A, dropping to <1A in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3447 ideally suited for single cell Li-Ion battery-powered applications. 100% duty cycle capability provides low dropout operation, extending battery life in portable systems. Automatic Burst Mode operation increases efficiency at light loads, further extending battery life. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode.
APPLICATIO S

, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
VIN 2.5V TO 5.5V
C2 4.7F CERAMIC
VIN
I2C
VCCD
PWREN C3 4.7F
PGOOD LTC3447 VCCD SW SDA SCL GND VOUT FB
RUN
EFFICIENCY (%)
10k SDA SCL
10k
* 600mA AT VIN = 3V
EXPOSED PADDLE TO GROUND
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TYPICAL APPLICATIO
Efficiency and Power Loss vs Load Current (VIN = 3.6V)
100
VIN
RPU1 20k
VOUT 0.69V TO 2.05V AT 600mA*
90 80 70 60 50 40 30 20 10 0
3447 TA01
L1 3.3H
C1 10F
R1 100k
R2 49.9k
1
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1000 POWER LOSS (mW) 100 10
PULSE SKIP EFFICIENCY Burst Mode EFFICIENCY LOSS
FEATURES
DESCRIPTIO
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10 100 LOAD CURRENT (mA)
1 1000
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1
LTC3447
(Note 1)
VIN, VCCD Voltages ....................................... -0.3V to 6V RUN, VOUT, FB Voltages .............................. - 0.3V to VIN SW Voltage ................................... -0.3V to (VIN + 0.3V) SCL, SDA Voltages ................................... - 0.3V to VCCD P-Channel Switch Source Current (DC) ...............800mA N-Channel Switch Sink Current (DC) ...................800mA Peak SW Sink and Source Current ...........................1.3A Operating Temperature Range (Note 2) ...-40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range...................-65C to 125C
TOP VIEW VOUT GND FB PGOOD VIN 1 2 3 4 5 11 10 SDA 9 VCCD 8 SCL 7 RUN 6 SW
ORDER PART NUMBER LTC3447EDD DD PART MARKING LBKB
DD PACKAGE 10-LEAD (3mm x 3mm)PLASTIC DFN EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 43C/W, JC = 2.96C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL RUN PGOOD RVOUT VOUT(MIN) VOUT(MAX) VOUT VOUT IPK VLOADREG VIN IS PARAMETER Run Threshold Reports Undervoltage Feedback Resistance Regulated Output Voltage Regulated Output Voltage Output Voltage Step Size (6-bits) Output Voltage Line Regulation Peak Inductor Current Output Voltage Load Regulation Input Voltage Range Input DC Bias Current Burst Mode Operation Active Mode Shutdown Nominal Oscillator Frequency RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET SW Leakage Optional Start-Up Feedback Voltage Feedback Input Current I2C Clock Logic Threshold I2C Clock Logic Hysteresis I2C Data Logic Threshold I2C Data Logic Hysteresis
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise specified.
CONDITIONS PGOOD = 0.4V

MIN 0.3 3 0.669 1.989 20.3
TYP 1 460 0.69 2.05 21.6 0.2 0.2 1 0.5
MAX 1.5
0.711 2.112 22.9 1.2 1 1.25 5.5
UNITS V mA k V V mV %/V %/V A % V A A A MHz kHz A V nA V mV V mV
VIN = 2.5V to 5.5V (Note 6) Duty Cycle < 35%, Wafer Level
0.75
2.5 34 280 0.1 1 160 0.32 0.22 0.1 0.6 2.5 VCCD/2 300 VCCD/2 300
fOSC RPFET RNFET ILSW FB IFB SCLTHR SCLHYST SDATHR SDAHYST
(Note 4) ILOAD = 0A VOUT = 90%, ILOAD = 0A VRUN = 0V, VIN = 5.5V VOUT = 100% VOUT = 0V ISW = 100mA, Wafer Level ISW = -100mA, Wafer Level VRUN = 0V, VSW = 0V or 5V, VIN = 5V Regulated Feedback Voltage (Note 5) (Note 5) (Note 5) (Note 5)
0.7
60 400 1 1.3
1 10
2
U
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W
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U
WW
W
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
LTC3447 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER I2C Interface Timing fI2C, MAX Maximum I2C Operating Frequency tBUF Bus Free Time Between Stop and Start Condition tHD,RSTA Hold Time After (Repeated) Start Condition tSU,RSTA Repeated Start Condition Setup Time tSU,STOP Stop Condition Setup Time tHD,DIN Data Hold Time, Input tHD,DOUT Data Hold Time, Output tSU,DAT Data Setup Time tSP Pulse Width of Spikes Suppressed by Input Filter
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise specified.
CONDITION (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) MIN TYP MAX 400 1.3 0.6 0.6 20 0 280 50 UNITS kHz s s s s ns ns ns ns
410
670 150
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3447E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature, TA, and the power dissipation, PD, according to the following formula: TJ = TA + PD * 43C/W
This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: Determined by design, not production tested. Note 6: The LTC3447 is tested in a proprietary test mode that connects VOUT to FB.
SDA tSU, DAT tHD, DAT tLOW SCL tHD, STA tr START COMMAND tHIGH tSU, STA tHD, STA tSU, STO tBUF
W
tf REPEATED START COMMAND STOP COMMAND START COMMAND
3447 F01
TI I G DIAGRA UW
Figure 1. Timing Diagram
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3
LTC3447 TYPICAL PERFOR A CE CHARACTERISTICS
DAC Nonlinearity
0.5 0.4 0.3 0.2 ERROR (LSB) 0.1 0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 0 10 20 30 DAC 40 50 60
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EFFICIENCY (%)
60 50 40 30 20 10 0 1
VOUTMIN
EFFICIENCY (%)
DNL
EffIciency and Power Loss vs Load Current (VIN = 2.5V)
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 1 10 100 LOAD CURRENT (mA) LOSSMAX LOSSMIN VOUTMAX VOUTMIN
100
VOUTMAX (V)
VIN = 2.5V 2.00 DAC = MIN VIN = 3.6V VIN = 2.5V 1.95 0.65 0.70
BIAS CURRENT (A)
1.12 1.10 1.08 FREQUENCY (MHz)
Frequency vs Supply Voltage
BIAS CURRENT (mA)
FREQUENCY (MHz)
1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 2.5 3.5 4.5 SUPPLY VOLTAGE (V) 5.5
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4
UW
INL
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Efficiency and Power Loss vs Load Current (VIN = 5.5V)
100 90 80 70 POWER LOSS (mW) 100 VOUTMAX 1000 100 90 80 70 60 50 40 30 20 10 10 100 LOAD CURRENT (mA) 1 1000
3447 GO1
EffIciency and Power Loss vs Load Current (VIN = 3.6V)
1000 VOUTMAX VOUTMIN POWER LOSS (mW) 100
LOSSMAX LOSSMIN 10
LOSSMAX LOSSMIN
10
0
1
10 100 LOAD CURRENT (mA)
1 1000
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1000
Output Voltage vs Load Current
2.10 0.80 350 300 2.05 DAC = MAX VIN = 3.6V 0.75 VOUTMIN (V) 250 200 150 100 50
Bias Current vs Supply Voltage
PULSE SKIP
POWER LOSS (mW)
10
1 1000
1.90
0
200
600 800 400 LOAD CURRENT (mA)
0.60 1000
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BURST 0 2.5
4.5 3.5 SUPPLY VOLTAGE (V)
5.5
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1.30 1.24 1.18 1.12 1.06 1.00 0.94 0.88 0.82 0.76
Frequency vs Temperature
360
Bias Current and Shutdown Current vs Temperature
BIAS CURRENT VIN = 5.5V VIN = 2.5V 3.0 2.5 SHUTDOWN CURRENT (A) 2.0 1.5 260 SHUTDOWN CURRENT VIN = 3.6V VIN = 2.5V VIN = 5.5V 1.0 0.5 0
VIN = 3.6V 310
210
0.70 -40 -20
0
20 40 60 80 100 120 TEMPERATURE (C)
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160 -40 -20
0
20
40
60
80 100 120
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TEMPERATURE (C)
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LTC3447 TYPICAL PERFOR A CE CHARACTERISTICS
RDS(ON) vs Supply Voltage
0.60 0.55 0.50 RDS(ON) () RDS(ON) () 0.45 0.40 0.35 0.30 0.25 0.20 2.5 3.5 4.5 5.5
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VOUTMAX (V)
PFET
NFET
SUPPLY VOLTAGE (V)
Feedback Reference vs Supply Voltage
610 618 612 605 606 VFB (V) 600 FB (V) 600 594 595 588 590
2.5
3.5 4.5 SUPPLY VOLTAGE (V)
Soft-Start with No Load
500mV/DIV
500mV/DIV VOUT 500mV/DIV
5V/DIV PGOOD 100mA/DIV 5V/DIV
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200mA/DIV INDUCTOR CURRENT 200s/DIV
UW
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RDS(ON) vs Temperature
0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C)
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Output Voltage vs Supply Voltage
2.060 2.055 2.050 DAC = MAX 0.720 0.715 0.710 0.705 0.700 DAC = MIN 0.695 0.690 0.685 3.5 4.5 SUPPLY VOLTAGE (V) 0.680 5.5
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VIN = 3.6V
PFET
2.045 2.040 2.035 2.030 2.025 2.020 2.5
VOUTMIN (V)
NFET
Feedback Voltage vs Temperature
Load Step (200mA to 400mA)
VOUT 50mV/DIV
LOAD CURRENT 200mA/DIV
5.5
582 -40 -20
0
20
40
60
80 100 120
3447 G15
40s/DIV
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TEMPERATURE (C)
VOUT(MIN) to VOUT(MAX) Transition
PULSE SKIP MODE VOUT 500mV/DIV
VOUT(MAX) to VOUT(MIN) Transition
BURST MODE OPERATION
VOUT INDUCTOR CURRENT 200mA/DIV INDUCTOR CURRENT PGOOD 100s/DIV
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5V/DIV
PGOOD 100s/DIV
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5
LTC3447 PI FU CTIO S
VOUT (Pin 1): Output Voltage Sensing Pin. An internal resistor divider provides the divided down feedback reference for comparison. GND (Pin 2): Ground for all Circuits Excluding the Internal Synchronous Power NFET. FB (Pin 3): Feedback Sensing Pin for the Optional External Feedback Resistors. Must be tied to VIN if there are no external feedback resistors. PGOOD (Pin 4): Fault Report. Open drain driver sinks current when VOUT is 10% out of tolerance. Blanking during DAC changes can be enabled via the I2C. VIN (Pin 5): Main Supply Pin. Must be closely decoupled to GND with a 2.2F or greater capacitor.
RUN VCCD SDA SCL
6-BIT DAC
VDAC
I2C
BURST
BLANK
DAC
LOAD
PGOOD
POWER GOOD
REF UV REF OV REF
LTC3447
3447 BD
6
W
BLOCK DIAGRA
U
U
U
SW (Pin 6): Switch Node Connector to Inductor. This pin connects the drains of the internal main and synchronous power MOSFET switches. RUN (Pin 7): Run Control Input. Forcing pin above 1.5V enables the part. Forcing the pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1A of supply current. Do not leave the RUN pin floating. SCL (Pin 8): I2C Clock Input. VCCD (Pin 9): I2C Power Rail. SDA (Pin 10): I2C Data Input. Exposed Pad (Pin 11): Ground. Must be connected to PCB ground for electrical contact and optimized thermal performance.
VIN
CIN
VOUT
+ -
SLEW SOFT-START
SW BUCK VREF REGULATOR VFB
SW
1.3R
COUT
BURST
MUX
R
R1
MUX FB
R2
S
DAC
Figure 2. LTC3447 High Level Block Diagram
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LTC3447
BUCK OPERATION
VFB EA VREF VIN
PEAK CURRENT LEVEL REF
OSC
BUCK REGULATOR
Figure 3. LTC3447 Buck Regulator Diagram
Main Control Loop The LTC3447 uses current mode step-down architecture with both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, FB, relative to an internal reference voltage, which in turn, causes the EA amplifier's output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Burst Mode Operation The LTC3447 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. Burst Mode operation can be disabled via the I2C interface. When Burst Mode operation is disabled, the regulator is in pulse skipping mode operation. During Burst Mode operation, the LTC3447's internal circuits sense when the inductor peak current falls below
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RS LATCH
S R Q QB
LOGIC BURST
NFET PFET
OPERATIO
ICOMP
RS
SW
50mA. When below this level, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 33A, and the peak current level reference level is held at 150mA. The LTC3447 remains in this sleep state until the output voltage falls below the output voltage setting. Once this occurs, the regulator wakes up and allows the inductor to develop 150mA current pulses. For light loads, this will cause the output voltage to increase and the internal peak current reference to decrease. When the peak current reference falls to below 50mA, the part re-enters sleep mode and the cycle is repeated. This process repeats at a rate that is dependent on the load demand. Pulse Skipping Mode Operation At light loads, the inductor current may reach zero or reverse on each pulse. The bottom MOSFET is turned off by the current reversal comparator, IRCMP, and the switch voltage will ring. This is discontinuous mode operation, and is normal behavior for a switching regulator. At very light loads, the LTC3447 will automatically skip pulses in pulse skipping mode operation to maintain output regulation. This feature is enabled when the Burst Mode operation is disabled. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 160kHz. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing thermal runaway. The oscillator's frequency will progressively increase to 1MHz when VOUT rises above 0V. Dropout Operation When using the optional external feedback resistors, it is possible for VIN to approach the output voltage level. As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore,
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IRCMP
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7
LTC3447
the user should calculate the power dissipation when the LTC3447 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). Low Supply Operation The LTC3447 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 4 shows the reduction in the maximum output current as a function of input voltage for various output voltages. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current
1200 MAXIMUM LOAD CURRENT (mA) TA = 25C DAC = MIN 1100 500mV/DIV
1000 DAC = MAX 900 200mA/DIV 800 5V/DIV 700 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5
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Figure 4. Maximum Load Current vs Supply Voltage
SDA
SCL S START COMMAND
ADDRESS
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for duty cycles >40%; however, the LTC3447 uses a patent-pending scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. DAC The I2C interface is used to control the internal voltage DAC for the buck regulator. The output voltage range is 0.69V to 2.05V in 21.6mV steps. The default DAC setting is 100000 which equates to a 1.38V output voltage. Output voltage transitions begin once the I2C interface receives the STOP command. Slew Rate The LTC3447 has a slew rate of approximately 11mV/s. The slew rate is controlled by the RC time constant of a low pass filter at the voltage DAC output. Figure 5 shows a typical transition from min to max DAC settings.
BURST MODE OPERATION VIN = 3.6V VOUT INDUCTOR CURRENT PGOOD 100s/DIV
OPERATIO
Figure 5.Transition from DAC = MIN to DAC = MAX
1-7
8
9
1-7
8
9
1-7
8
9 P
R/W
ACK
DATA
ACK
DATA
ACK
ST0P COMMAND
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Figure 6. Typical I2C Write Protocol
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LTC3447
External Start-Up Option The LTC3447 allows for the use of optional external resistors to determine the start-up voltage. Using this option, the start-up voltage can be set to levels inside or outside the DAC output's operating range. The output voltage will be regulated at this value until the internal DAC is updated and a STOP command is received. Once the STOP command is received, the internal DAC will retain control of the output voltage until the part is disabled then enabled again. If this feature is not used, the feedback pin must be tied to VIN. I2C OPERATION Typical 2-wire serial I2C Serial interface Simple 2-wire interface Multiple devices on same bus Idle bus must have SDA and SCL lines high LTC3447 is write only Master controls bus Devices listen for unique address that precedes data General I2C Bus/SMBus Description I2C Bus and SMBus are reasonably similar examples of two wire, bidirectional, serial communications busses. Calling them two wire is not strictly accurate, as there is an implied third wire, which is the ground line. Large ground drops or spikes between the grounds of different parts on the bus can interrupt or disrupt communications, as the signals on the two wires are both inherently referenced to a ground which is expected to be common to all parts on the bus. Both bus types have one data line and one clock line which are externally pulled to a high voltage when they are not being controlled by a device on the bus. The devices on the bus can only pull the data and clock lines low, which makes it simple to detect if more than one device is trying to control the bus; eventually, a device will release a line and it will not pull high because another device is still holding it low. Pull-ups for the data and clock lines are usually provided by external discrete resistors, but external current sources can also be used. Since there are no dedicated lines to use to tell a given device if another device is trying to communicate with it, each device must have a unique address to which it will respond. The first part of any communication is to send
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out an address on the bus and wait to see if another device responds to it. After a response is detected, meaningful data can be exchanged between the parts. Typically, one device will control the clock line at least most of the time and will normally be sending data to the other parts and polling them to send data back to it, and this device is called the master. There can certainly be more than one master, since there is an effective protocol to resolve bus contentions, and nonmaster (slave) devices can also control the clock to delay rising edges and give themselves more time to complete calculations or communications (clock stretching). Slave devices need to be able to control the data line to acknowledge communications from the master, and some devices will need to able to send data back to the master; they will be in control of the data line while they are doing so. Many slave devices will have no need to stretch the clock signal and will have no ability to pull the clock line low, which is the case with the LTC3447. Data is exchanged in the form of bytes, which are 8-bit packets. Every byte needs to be acknowledged by the slave (data line pulled low) or not acknowledged by the master (data line left high), so communications are broken up into 9-bit segments, one byte followed by one bit for acknowledging. For example, sending out an address consists of 7-bits of device address, 1-bit that signals whether a read or write operation will be performed, and then 1 more bit to allow the slave to acknowledge. There is no theoretical limit to how many total bytes can be exchanged in a given transmission. I2C and SMBus are very similar specifications, SMBus having been derived from I2C. In general, SMBus is targeted toward low power devices (particularly battery powered ones) and emphasizes low power consumption, while I2C is targeted toward higher speed systems where the power consumption of the bus is not so critical. I2C has three different specifications for three different maximum speeds, these being standard mode (100kHz max), fast mode (400kHz max), and HS mode (3.4MHz max). Standard and fast mode are not radically different, but HS mode is very different from a hardware and software perspective and requires an initiating command at standard or fast speed before data can start transferring at HS speed. SMBus simply specifies a 100kHz maximum speed.
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OPERATIO
9
LTC3447
The START and STOP Commands When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START command by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP command by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Acknowledge The acknowledge signal is used for handshaking between the master and the slave. An acknowledge signal (LOW active) is generated by the slave lets the master know that the latest byte of information was received. The acknowledge-related clock pulse is generated by the master. The transmitter master releases the SDA line (HIGH) during the acknowledge clock pulse. The slave receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave receiver doesn't acknowledge the slave address (for example, it's unable to receive because it's performing some real-time function), the data line must
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be left HIGH by the slave. The master can then generate a STOP command to abort the transfer. If a slave receiver does acknowledge the slave address but, some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP command. The data line is also left high by the slave and master after a slave has transmitted a byte of data to the master in a read operation, but this is a not acknowledge that indicates that the data transfer is successful. Commands Supported The LTC3447 supports only write byte commands to a single register. During ACK bit periods, the LTC3447 will pull the data line low to acknowledge the master device. See Figure 7. Data Transfer Timing for Write Commands In order to help assure that bad data is not written into the part, data from a write command is only stored after a valid STOP command has been performed.
WRITE BYTE PROTOCOL 1 START 7 1100110 SLAVE ADDRESS 1 0 WRITE I2C REGISTER DEFINITION MSB 7 DISABLE BURST (DEFAULT = 0) 6 5 4 3 2 1 0 LSB 1 ACK 8 XXXXXXXX DATA 1 ACK 1 STOP ENABLE BUCK BUCK BUCK BUCK BUCK BUCK DAC2 PGOOD DAC5 DAC4 DAC3 DAC1 DAC0 BLANKING (DEFAULT = 1) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) (DEFAULT = 0) 3447 F07
OPERATIO
Figure 7. LTC3447's Write I2C Protocol
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LTC3447
Table 1. I2C Fast-Mode Timing Specifications (for Reference)
fI2C tBUF tHD,RSTA tSU,RSTA tSU,STOP tHD,DAT tSU,DAT tLOW tHIGH tSP tf tr I2C Operating Frequency Bus free time between Stop and Start Condition Hold Time after (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Pulse Width of Spikes Suppressed by Input Filter Clock, Data Fall Time Clock, Data Rise Time 0 1.3 0.6 0.6 0.6 0 100 1.3 0.6 0 20 + 0.1 * CB 20 + 0.1 * CB 400 kHz s s s s ns ns s s ns ns ns
CB = Capacitance of one bus line.
The basic LTC3447 application circuit is shown on the front page of the data sheet. External component selection is driven by the load requirement and begins with the selection of L1 followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1H to 4.7H. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current is IL = 240mA (40% of 600mA). 1 V IL = VOUT 1 - OUT (f)(L) VIN(MAX) (1) The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 920mA rated inductor should be enough for most applications (800mA + 120mA). For better efficiency, choose a low DC resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 50mA. Lower inductor values (higher IL) will cause this
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APPLICATIO S I FOR ATIO W UU
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0.9 50 300 300
OPERATIO
to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or perm alloy materials are small and don't radiate much energy, but generally cost more than powdered-iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price versus size requirements and any radiated field/EMI requirements than on what the LTC3447 requires to operate. Table 2 shows some typical surface mount inductors that work well in LTC3447 applications.
Table 2.
Manufacturer Value DCR Max DC Part Number (H) (m max) Current (A) Sumida 3.3 85 1.4 CDRH3D16/HP3R3 Sumida 4.7 109 1.15 CR434R7 Murata 2.2 29 3.2 LQH55DN2R2MO3 Toko 2.2 59 1.63 D52LC-A914BYW-2R2M Size W x L x H (mm3) 4.0 x 4.0 x 1.8 4.0 x 4.5 x 3.5 5.0 x 5.0 x 4.7 5.0 x 5.0 x 2.0
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LTC3447
CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: [VOUT (VIN - VOUT )]1/ 2 CIN required IRMS IOMAX VIN (2) This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple VOUT is determined by: 1 VOUT IL ESR + 8fC OUT (3) where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now
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becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3447's control loop does not depend on the output capacitor's ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The LTC3447 has an internal resistor divider network tied to the OUT pin. The output voltage is controlled by a DAC (6-bit register) whose setting is programmed via the I2C interface. The DAC controls the VOUT range of 0.69V to 2.05V in 21.6mV steps. The default value for VOUT is 1.38V and is reset to this value whenever VIN comes up. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3447 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R
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APPLICATIO S I FOR ATIO W UU
LTC3447
loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 8.
1
POWER LOSS (mW)
0.1
0.01 DAC = MAX
DAC = MIN 1000
3447 F08
0.001
0.1
1
10 100 LOAD CURRENT (mA)
Figure 8. Power Loss vs Load Current
The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to
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RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 * CLOAD). Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA. Thermal Considerations In most applications the LTC3447 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3447 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3447 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum
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LTC3447
junction temperature of the part. The temperature rise is given by: TR = JA * PD where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3447 when using an input voltage of 3.6V, an ambient temperature of 70C, and a buck load current of 500mA. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70C is approximately 0.45. Therefore, power dissipated by the part is: PD = ILOAD2 * RDS(ON) = 112.5mW For the DFN-10 package, the JA is 43C/W. Thus, the junction temperature of the regulator is: TJ = 70C + (0.1125)(43) = 74.8C which is well below the maximum junction temperature of 150C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3447. These items are also illustrated graphically in Figures 9 and 10. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace, and the VIN trace should be kept short, direct and wide. 2. Does the VOUT pin connect directly to the output voltage reference? Ensure that there is no load current running from the output voltage and the VOUT sense pin. 3. Does the FB pin connect directly to the feedback voltage reference? Ensure that there is no load current running from the feedback reference voltage and the FB pin. 4. Does the (+) plate of CIN connect to VIN as closely as
R1
GND VCCD
R2
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possible? This capacitor provides the AC current to the internal power MOSFETs. 5. Keep the switching node, SW, away from the sensitive VOUT and FB nodes. 6. Keep the (-) plates of CIN and COUT as close as possible.
GND PLANE
R1
APPLICATIO S I FOR ATIO W UU
C2
VOUT
SDA
GND
VCCD
FB
SCL
PGOOD
RUN
VIN
VIN
CIN
SW
L1
GND PLANE
COUT
VIA TO VOUT
3447 F09
Figure 9. LTC3447 Suggested Layout
VOUT
SDA
R2
FB SCL
C2
PGOOD
RUN
VIN
CIN
SW
COUT
L1
VIN
VOUT
3447 F11
Figure 10. LTC3447 Layout Diagram
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LTC3447
Design Example As a design example, assume the LTC3447 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The normal load current requirement is a maximum of 500mA at 1.4V, but most of the time it will be in standby mode, requiring only 200A at 1V. Efficiency at both low and high load currents is important. To ensure that the ripple currents and voltages do not exceed desired expectations over the DAC output range, calculations with maximum VIN and minimum VOUT should be used. Note that either increasing the output voltage or decreasing VIN will result in a decrease of ripple current and voltage. Choosing a maximum ripple current, IL, of 280mA, Equation 1 can be used to determine the size of the inductor that should be used. 1 1.4V L= * 1.4V 1 - = 3.3H 4.2V (1MHz)(280mA)
EFFICIENCY (%)
A 3.3H inductor works well for this application. For best efficiency choose a 640mA or greater inductor with less than 0.2 series resistance. CIN will require an RMS current of at least 0.25A, approximately ILOAD(MAX)/2, overtemperature (see Equation 2). For COUT, selecting a 4.7F capacitor with an ESR of 0.25 yields the following ripple voltage using Equation 3.
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.675 0.05
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES)
0.25 0.05
0.50 BSC 2.38 0.05 (2 SIDES)
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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PACKAGE DESCRIPTIO
DD Package 10-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 0.38 0.10
PACKAGE OUTLINE
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1 VOUT = 0.280 A 0.25 + = 8(1MHz)(4.7F) 70mV + 7.4mV = 77.4mV Note that the majority of the ripple voltage is generated by the capacitor's ESR. Most ceramic capacitors will have a typical ESR of 10m or less. Selecting capacitors with low ESRs will significantly reduce the ripple voltage. Efficiency can be improved by taking advantage of the LT3447's Burst Mode operation. When entering the standby mode, ensure that the burst disable bit is set to 0 when the output voltage DAC is updated. Likewise, when entering a heavy current load mode, ensure the burst disable bit is set to 1 when the output voltage DAC is updated. Figure 11 shows the advantage of utilizing the Burst Mode function.
100 90 80 70 60 50 40 30 20 10 0 0.1
APPLICATIO S I FOR ATIO W UU
STBY
DAC(MAX)
DAC(MAX)
NORMAL
DAC(MIN)
DAC(MIN)
1 10 100 LOAD CURRENT (mA)
BURST PSK
1000
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Figure 11. Efficiency vs Load Current ( VIN = 4.2V)
6
10
3.00 0.10 (4 SIDES)
1.65 0.10 (2 SIDES)
PIN 1 TOP MARK (SEE NOTE 6)
0.200 REF
0.75 0.05
5 2.38 0.10 (2 SIDES)
1
(DD10) DFN 1103
0.25 0.05 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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LTC3447 U
Li-Ion Battery to 1.4V/1V Regulator
Li Ion BATTERY
TYPICAL APPLICATIO
20k
CIN 4.7 F
VIN
FB LTC3447 PGOOD VOUT RUN VCCD SW
L1 3.3 H
VOUT = COUT 4.7 F
1.4V AT 500mA IN NORMAL OPERATION 1V AT 200 A IN STBY MODE
I2C BUS
VCCD
PWREN
10k SDA SCL
10k
4.7 F
SDA SCL GND
CIN, COUT: TDK C1608X5R0J475MT L1: SUMIDA CDRH3D16-3R3
EXPOSED PADDLE TO GROUND
3447 TA02
RELATED PARTS
PART NUMBER LT1761 DESCRIPTION 100mA, Low Noise Micropower, LDO COMMENTS VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 20A, ISD < 1A, VOUT = Adj, 1.5V, 1.8V, 2V, 2.5V, 2.8V, 3V, 3.3V, 5V, ThinSOTTM Package. Low Noise < 20VRMS(P-P), Stable with 1F Ceramic Capacitors VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 25A, ISD < 1A, VOUT = Adj, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20VRMS(P-P) VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.30V, IQ = 30A, ISD < 1A, VOUT = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, S8 Package. Low Noise < 20VRMS(P-P) VIN: 6.5V to 1.6V, VOUT(MIN) = 1.25V, Dropout Voltage = 0.08V, IQ = 40A, ISD < 1A, VOUT = Adj, 1.5V, 1.8V, 2.5V, 2.8V, 3.3V, ThinSOT Package. Low Noise < 30VRMS(P-P), Stable with 1F Ceramic Capacitors VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, Dropout Voltage = 0.27V, IQ = 30A, ISD < 1A, VOUT = 1.5V, 1.8V, 2.5V, 3V, 3.3V, 5V, MS8 Package. Low Noise < 20VRMS(P-P) VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, Dropout Voltage = 0.15V, IQ = 120A, ISD < 1A, VOUT = Adj, DFN Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD < 1A, ThinSOT Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD < 1A, ThinSOT Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, MS10E, QFN Packages VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, MS10 Package VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, TSSOP16E Package VIN: 2.5V to 5.5V, VOUT = 0.85V to 1.55V, IQ = 27A, ISD < 1A, Two LDOs I2C Interface, Back-Up Battery Management, QFN24 VIN: 3V to 5.5V, Seamless Transition Between Input Sources and Li-Ion Battery, USB, 5V Wall Adapter, QFN24 Package Standalone Charger, Automatic Switchover when Input Supply is Removed More Efficient than Diode ORing
3447f LT/TP 0505 500 * PRINTED IN USA
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300mA, Low Noise Micropower, LDO Low VIN (0.9V) Low VOUT (0.2V) VLDOTM 300mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz Synchronous Step-Down DC/DC Converter Dual 600mA, 1.5MHz Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter, 600mA, 1.5MHz Synchronous Step-Down DC/DC Converter with Two LDOs and PowerPathTM Manager Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger USB Power Manager and Li-Ion Battery Charger PowerPath Controllers in ThinSOT
LT3020 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3411 LTC3412 LTC3445 LTC3455 LTC4055 LTC4411/LTC4412
ThinSOT, VLDO and PowerPath are trademarks of Linear Technology Corporation.
16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2005

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